1. Field of the invention
The present invention relates to a grid array type lead frame and a lead end grid array semiconductor package employing the same. More particularly, the present invention relates to a grid array type lead frame having a plurality of leads classified into groups by length, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-converting lead part is formed by at least one bending part, thereby distributing lead ends in a grid array, and a lead end grid array semiconductor package employing the same, which is as small as or similar to that of a semiconductor chip in area while a plurality of leads extend to lead ends which are arrayed on one plane, a farther distance away from neighboring ones but in a higher number per area, in such a manner that they form a grid array, and to lead end grid array semiconductor packages employing the same.
2. Description of the Prior Art
To encapsulate semiconductor chips and their peripheral parts with plastics such as epoxy resins with the aim of protecting them from external environment is of relatively low cost as well as of high efficiency. By virtue of these advantages, such encapsulation is widely applied in quad flat semiconductor packages, which have leads extending from the same plane in all four side directions and in ball grid array semiconductor packages, which utilize solder balls as input and output ends.
However, such a conventional quad flat semiconductor package is difficult to reduce in size because the leads are in the same plane as the plastic encapsulating part and extend from the four sides of the package to its exterior. In addition, the high integration of semiconductor chips requires an exceptionally increased number of pins the distance between which has been technically difficult to narrow to a certain value. Thus, to accommodate such a large number of pins, a large-sized package is necessary, which results in retrogradation against the tendency toward the small size of semiconductor packages.
In an effort to solve such a multi-pin problem, there has been suggested a ball grid array semiconductor package that utilizes as input and output ends a plurality of solder balls fused into the bottom of a substrate. Not only can the ball grid array semiconductor package accommodate far more numbers of input and output signals, but can be smaller in size than the quad flat semiconductor package.
In spite of these advantage, there has still been a significant limit in the reduction of the size of the ball grid array semiconductor package because the circuit board used is far larger than the semiconductor chip. In addition, the circuit board is so expensive that the price of the product could be adversely affected.
In U.S. Pat. No. 5,363,279 a semiconductor package having a decreased package area is disclosed in which the leads electrically connected with the semiconductor chips do not extend to the side of the package but are introduced to the package bottom below the semiconductor chip mounting area, as shown in FIGS. 22A and 22B. In FIG. 22A, a schematic cross section is shown for a package 100 of such a conventional lead frame having a plurality of double-bent leads 102 lining up in a double file with the same length, a semiconductor chip 120 attached to a non-bent area of the leads 102 by an adhesive means 150, bond wires 130 electrically connecting the leads 102 with the semiconductor chip 120, and an encapsulating part 140 for protecting the above-mentioned elements from the external environment. For the miniaturization of the package 100, the ends 104 of the bent leads 102 are arrayed in two rows on the bottom of the encapsulating part 140 below a semiconductor chip-mounting area without projecting them externally.
FIG. 22B shows the bottom of the package 100 on which the lead ends 104 are exposed lining up in a double file. This structure successfully provides for miniaturization to the package 100 but has a serious problem in that the number of the leads playing as input and output ends is rather fewer than that of the leads in the conventional quad flat semiconductor package. If the number of the exposed lead ends 104 arrayed in two rows is increased per area, when the package is mounted on a mother board (not shown) by soldering, a package defect would be highly apt to occur wherein the resulting narrow distance between the neighboring lead ends leads to either a short circuit or a signal interference to which a noise is attributed, resulting in the difficulty in transmitting signals at high speed. Thence, it is virtually difficult to increase the number of the exposed lead ends 104 in the conventional package 100.
Japanese Patent Laid-Open Publication No. 6-53399 discloses a semiconductor device encapsulated in a resin, which comprises a plurality of leads bent in a U form. This is shown in FIG. 22A. As shown, leads 202 all extend to all four side directions of a semiconductor chip and the lower part of each of them is exposed on the bottom of a resin encapsulating part. FIG. 23B is a bottom view of a package 200 of FIG. 22A. As seen in FIG. 23B, the leads 202 are arrayed in a line along the four sides of the package at the outside of the chip mounting area, totally forming a square. The miniaturization of the package 200 as well as the increase in the number of the exposed lead ends 202 per area is impossible to realize in practice.